IP Design Lead, Networking, Google Cloud

Minimum qualifications Bachelor's degree in Electrical Engineering or equivalent practical experience. 10 years of experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language. 8 years of experience in managing teams and groups. Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability. Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.