Package Design/Layout Engineer

Minimum qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with functional tests for silicon validation (i.e., writing in C or C++ or Python or similar). 5 years of experience in pre-silicon or post-silicon validation. 5 years of experience in silicon bring-up, functional validation, characterizing, and qualifying silicon.