Physical Design Engineer, SoC Static Timing Analysis

Minimum qualifications Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience. 8 years of Physical Design experience including 5 years of experience with Static Timing Analysis (STA), including sign-off corner definitions, process margining, interface timing constraints, timing convergence, and setting frequency goals with technology scaling. Experience in constraints development for subsystems or full System-on-Chip (SoC) architectures.